Course code: VIAVI-1

Years with company: 11

Years programming: 18

Primary programming language: Verilog

Other programming languages: TCL, Python, Perl

Unit test harnesses: none

Something else: FPGA Engineer who hasn't done much SW coding since school

Test practice now: In system debug and simulation

Target system: Custom hardware

Dev tools: Vendor provided tools

Build time: 5-30 minutes

Coding standard: Mostly follow existing code

Function too long: I don't.

Code reviews: Performed based on who is doing the coding

Code time: 50

Test time: 10

Debug time: 30

Favorite thing about dev: N/A

Least favorite thing about dev: N/A

Tdd knowledge: It's supposed to be iterative and fast

Why are you attending: To see if there are any concepts/techniques that can be applied to FPGA development.