Course code: SP-CPP-3

Years with company: 5

Years programming: 20

Primary programming language: C

Other programming languages: C++, Python, VHDL, Verilog, System Verilog

Unit test harnesses: Cppunit

Something else: I am also a course instructor and I also write technical blogs over at embeddedrelated.com :)

Test practice now: For C++ code Cppunit and using mocks for hardware drivers. For FPGA I use System Verilog with assertions to implement TDD to verify behaviours to reduce the risk of regressions when making changes.

Target system: Almost all my projects have an FPGA and chips around them that we interface to.

Dev tools: VSCode with TerosHDL for FPGA work and VSCode with C/C++ extensions for linting/code completion etc.

Build time: 1-5 minutes

Coding standard: I have formulated my own coding standards based on the DO aviation standard for FPGA's. For C MISRA.

Function too long: When it handles too many behaviours.

Code reviews: Generally I like to use checklists and have reviewers read standards beforehand.

Code time: 2

Test time: 4

Debug time: 4

Favorite thing about dev: It is always a joy to see new behaviours working on a live board.

Least favorite thing about dev: How much time is spent trying things until it works and how brittle it often is.

Tdd knowledge: Very little, just that it can help prevent regression issues using a design for test philosophy.

Why are you attending: I was recommended it by Steve Branam and most recently I'm finding it could be useful for FPGA's.